A pulse monitor circuit detects the presence or non-presence of the output pulses output from an output stage circuit. The pulse monitor circuit outputs an up signal to the up/down counter when the output pulses do not exist at all and outputs a down signal to the up/down counter when the output pulses exist. The up/down counter outputs a signal for increasing the delay amount of a delay amount variable circuit when a count value is large, that is, when the output pulses disappear. In contrast, when the count value is small, that is, when the output pulses exist, the counter outputs the signal for reducing the delay amount of the delay amount variable circuit.