A memory cell includes double-gate first and second access devices configured to selectively interconnect cross-coupled inverters with true and complementary bit lines. Each access device has a first gate connected to a READ word line and a second gate connected to a WRITE word line. During a READ operation, the first and second access devices are configured to operate in a single-gate mode with the READ word line “ON” and the WRITE word line “OFF” while the double-gate pull-down devices are configured to operate in a double gate mode. During a WRITE operation, the first and second access devices are configured to operate in a double-gate mode with the READ word line “ON” and the WRITE word line also “ON.”