Invention Grant
- Patent Title: Nonvolatile semiconductor memory and method for testing the same
- Patent Title (中): 非易失性半导体存储器及其测试方法
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Application No.: US12591878Application Date: 2009-12-03
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Publication No.: US07990778B2Publication Date: 2011-08-02
- Inventor: Satoru Oku
- Applicant: Satoru Oku
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-311970 20081208
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a trimming code output circuit that outputs any one of plural trimming codes to the voltage generator circuit. The plural trimming codes include a test trimming code in addition to an appropriate trimming code for generating a desired drive voltage. The test trimming code is different from the appropriate trimming code, and used only in the test state. In the test state, the trimming code output circuit outputs the test trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the test trimming code. In states other than the test state, the trimming code output circuit outputs the appropriate trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the appropriate trimming code.
Public/Granted literature
- US20100142289A1 Nonvolatile semiconductor memory and method for testing the same Public/Granted day:2010-06-10
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