Provided is tamper detection line circuitry for an authentication integrated circuit for use in authenticating an integrated circuit. The tamper detection line circuitry includes a source of pseudo-random bits, and an XOR gate with two inputs and an output in signal communication with flash memory erase and reset circuits. A complete erasure of the memory is triggered by a 0 from the XOR gate. The circuitry also includes first and second paths arranging the source and XOR gate in signal communication with each other, as well as a number of triggers connected to the respective paths, each trigger configured to detect a physical attack on the authentication integrated circuit, said triggers configured to pull a respective path to 0 if a physical attack is detected.