The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic.