Invention Grant
- Patent Title: In-memory, in-page directory cache coherency scheme
- Patent Title (中): 内存中,页内目录缓存一致性方案
-
Application No.: US12006326Application Date: 2007-12-31
-
Publication No.: US07991963B2Publication Date: 2011-08-02
- Inventor: Ian M. Steiner , Zhong-Ning George Cai , Saurabh Tiwari , Kai Cheng
- Applicant: Ian M. Steiner , Zhong-Ning George Cai , Saurabh Tiwari , Kai Cheng
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.
Public/Granted literature
- US20090172295A1 In-memory, in-page directory cache coherency scheme Public/Granted day:2009-07-02
Information query