Invention Grant
US07992059B2 System and method for testing a large memory area during processor design verification and validation
失效
在处理器设计验证和验证期间测试大内存区域的系统和方法
- Patent Title: System and method for testing a large memory area during processor design verification and validation
- Patent Title (中): 在处理器设计验证和验证期间测试大内存区域的系统和方法
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Application No.: US11853212Application Date: 2007-09-11
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Publication No.: US07992059B2Publication Date: 2011-08-02
- Inventor: Divya Subbarao Anvekar , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor
- Applicant: Divya Subbarao Anvekar , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: VanLeeuwen & VanLeeuwen
- Agent Matthew B. Talpis
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/00

Abstract:
A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.
Public/Granted literature
- US20090070643A1 System and Method for Testing a Large Memory Area During Processor Design Verification and Validation Public/Granted day:2009-03-12
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