Invention Grant
- Patent Title: Congestion estimation for programmable logic devices
- Patent Title (中): 可编程逻辑器件的拥塞估计
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Application No.: US12323974Application Date: 2008-11-26
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Publication No.: US07992120B1Publication Date: 2011-08-02
- Inventor: Xinyu Wang , Bo Wang
- Applicant: Xinyu Wang , Bo Wang
- Applicant Address: US OR Hillsboro
- Assignee: Lattice Semiconductor Corporation
- Current Assignee: Lattice Semiconductor Corporation
- Current Assignee Address: US OR Hillsboro
- Agency: Haynes and Boone, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Various techniques are provided for estimating signal congestion in a programmable logic device (PLD). In one example, a computer-implemented method of estimating signal congestion in routing resources of a PLD is provided. The routing resources comprise a plurality of nodes and a plurality of wires which may be selectively interconnected to provide a plurality of signal paths through the routing resources of the PLD. The method includes determining a plurality of wire congestion values. Each of the wire congestion values identifies a relative likelihood of a corresponding one of the wires being used to provide the signal paths in comparison with the other wires. The method also includes selecting a region of the routing resources. The method further includes determining a congestion density estimate for the region using the wire congestion values associated with the wires of the region.
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