Invention Grant
US07992122B1 Method of placing and routing for power optimization and timing closure
有权
放置和布线功能优化和时序收敛的方法
- Patent Title: Method of placing and routing for power optimization and timing closure
- Patent Title (中): 放置和布线功能优化和时序收敛的方法
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Application No.: US11093713Application Date: 2005-03-25
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Publication No.: US07992122B1Publication Date: 2011-08-02
- Inventor: Michael Burstein , Boris Ginzburg
- Applicant: Michael Burstein , Boris Ginzburg
- Applicant Address: US CA San Jose
- Assignee: GG Technology, Inc.
- Current Assignee: GG Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: The Law Offices of Andrew D. Fortney
- Agent Andrew D. Fortney
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing signal paths in one or more upper metal layers for connecting circuit blocks; (ii) adjusting the circuit blocks based on electrical characteristics of the signal paths; and (iii) routing in one or more lower metal layers connections between the circuit blocks and the upper layers. The circuit blocks can include standard cells, blocks, or gates configured to implement a logic or timing function, other components, and/or integrated circuits, for example. Embodiments of the present invention can advantageously reduce power consumption and improve timing closure in an automated place-and-route flow.
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