Invention Grant
US07993504B2 Backside unlayering of MOSFET devices for electrical and physical characterization
有权
用于电气和物理表征的MOSFET器件的背面非层叠
- Patent Title: Backside unlayering of MOSFET devices for electrical and physical characterization
- Patent Title (中): 用于电气和物理表征的MOSFET器件的背面非层叠
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Application No.: US12027563Application Date: 2008-02-07
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Publication No.: US07993504B2Publication Date: 2011-08-09
- Inventor: Terence L. Kane , Darrell L. Miles , John D. Sylvestri , Michael P. Tenney
- Applicant: Terence L. Kane , Darrell L. Miles , John D. Sylvestri , Michael P. Tenney
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: DeLio & Peterson, LLC
- Agent Kelly M. Nowak; Steven Capella
- Main IPC: C23C14/34
- IPC: C23C14/34

Abstract:
A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
Public/Granted literature
- US20080128086A1 BACKSIDE UNLAYERING OF MOSFET DEVICES FOR ELECTRICAL AND PHYSICAL CHARACTERIZATION Public/Granted day:2008-06-05
Information query
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