Invention Grant
US07993535B2 Robust self-aligned process for sub-65nm current-perpendicular junction pillars
有权
用于sub-65nm电流垂直连接柱的鲁棒自对准工艺
- Patent Title: Robust self-aligned process for sub-65nm current-perpendicular junction pillars
- Patent Title (中): 用于sub-65nm电流垂直连接柱的鲁棒自对准工艺
-
Application No.: US11627824Application Date: 2007-01-26
-
Publication No.: US07993535B2Publication Date: 2011-08-09
- Inventor: Xin Jiang , Stuart Stephen Papworth Parkin , Jonathan Sun
- Applicant: Xin Jiang , Stuart Stephen Papworth Parkin , Jonathan Sun
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: F. Chau & Associates LLC
- Agent Stephen C. Kaufman, Esq.
- Main IPC: H01B13/00
- IPC: H01B13/00 ; C03C15/00 ; C03C25/68 ; C23F1/00 ; B44C1/22 ; H01L21/302 ; H01L21/461
Abstract:
A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.
Public/Granted literature
- US20100330707A1 Robust Self-Aligned Process for Sub-65nm Current-Perpendicular Junction Pillars Public/Granted day:2010-12-30
Information query
