Invention Grant
US07993971B2 Forming a 3-D semiconductor die structure with an intermetallic formation
有权
形成具有金属间化合物的3-D半导体管芯结构
- Patent Title: Forming a 3-D semiconductor die structure with an intermetallic formation
- Patent Title (中): 形成具有金属间化合物的3-D半导体管芯结构
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Application No.: US11966126Application Date: 2007-12-28
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Publication No.: US07993971B2Publication Date: 2011-08-09
- Inventor: Ritwik Chatterjee , Eddic Acosta , Varughese Mathew
- Applicant: Ritwik Chatterjee , Eddic Acosta , Varughese Mathew
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer.
Public/Granted literature
- US20090170246A1 FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FORMATION Public/Granted day:2009-07-02
Information query
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