Invention Grant
- Patent Title: Wafer level die integration and method therefor
- Patent Title (中): 晶圆级芯片集成及其方法
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Application No.: US12042026Application Date: 2008-03-04
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Publication No.: US07993972B2Publication Date: 2011-08-09
- Inventor: Yaojian Lin , Haijing Cao
- Applicant: Yaojian Lin , Haijing Cao
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.
Public/Granted literature
- US20090224391A1 Wafer Level Die Integration and Method Therefor Public/Granted day:2009-09-10
Information query
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