Invention Grant
US07993976B2 Semiconductor device and method of forming conductive vias with trench in saw street
有权
半导体器件及其在沟道中形成具有沟槽的导电通孔的方法
- Patent Title: Semiconductor device and method of forming conductive vias with trench in saw street
- Patent Title (中): 半导体器件及其在沟道中形成具有沟槽的导电通孔的方法
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Application No.: US12484143Application Date: 2009-06-12
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Publication No.: US07993976B2Publication Date: 2011-08-09
- Inventor: Byung Tai Do , Reza A. Pagaila
- Applicant: Byung Tai Do , Reza A. Pagaila
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be stacked and electrically interconnected through the TSVs.
Public/Granted literature
- US20100317153A1 Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street Public/Granted day:2010-12-16
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