Invention Grant
- Patent Title: Transistor device with two planar gates and fabrication process
- Patent Title (中): 具有两个平面栅极和制造工艺的晶体管器件
-
Application No.: US11698755Application Date: 2007-01-26
-
Publication No.: US07994008B2Publication Date: 2011-08-09
- Inventor: Romain Wacquez , Philippe Coronel , Damien Lenoble , Robin Cerutti , Thomas Skotnicki
- Applicant: Romain Wacquez , Philippe Coronel , Damien Lenoble , Robin Cerutti , Thomas Skotnicki
- Applicant Address: FR Crolles Cedex
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles Cedex
- Agency: Gardere Wynne & Sewell LLP
- Agent Andre M. Szuwalski
- Priority: FR0600970 20060203
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
Public/Granted literature
- US20070194355A1 Transistor device with two planar gates and fabrication process Public/Granted day:2007-08-23
Information query
IPC分类:
