Invention Grant
- Patent Title: NMOS transistor devices and methods for fabricating same
- Patent Title (中): NMOS晶体管器件及其制造方法
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Application No.: US12763403Application Date: 2010-04-20
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Publication No.: US07994015B2Publication Date: 2011-08-09
- Inventor: Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
- Applicant: Sunderraj Thirupapuliyur , Faran Nouri , Yonah Cho
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agent Alan Taboada; Moser Taboada
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.
Public/Granted literature
- US20100264470A1 NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME Public/Granted day:2010-10-21
Information query
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