Invention Grant
- Patent Title: Method to reduce MOL damage on NiSi
- Patent Title (中): 减少NiSi上MOL损伤的方法
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Application No.: US12366378Application Date: 2009-02-05
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Publication No.: US07994038B2Publication Date: 2011-08-09
- Inventor: Karthik Ramani , Paul R. Besser
- Applicant: Karthik Ramani , Paul R. Besser
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong Mori & Steiner, P.C.
- Main IPC: H01L21/3205
- IPC: H01L21/3205

Abstract:
Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.
Public/Granted literature
- US20100193876A1 METHOD TO REDUCE MOL DAMAGE ON NiSi Public/Granted day:2010-08-05
Information query
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