Invention Grant
- Patent Title: Method of manufacturing stacked semiconductor package using improved technique of forming through via
- Patent Title (中): 使用改进的通孔形成技术制造堆叠半导体封装的方法
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Application No.: US12410387Application Date: 2009-03-24
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Publication No.: US07994041B2Publication Date: 2011-08-09
- Inventor: Kwon-Seob Lim , Hyun Seo Kang
- Applicant: Kwon-Seob Lim , Hyun Seo Kang
- Applicant Address: KR
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR
- Agency: Blakely, Sokoloff, Taylor & Zafman
- Priority: KR10-2008-0081330 20080820
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/4763 ; H01L21/00

Abstract:
A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is provided. The method includes forming a seed layer required for forming a via core on a bottom surface of a wafer, forming at least one via hole vertically through the wafer, forming a via core in the via hole, insulating the via hole from the via core, and removing the seed layer from the bottom surface of the wafer. The stacked semiconductor package is suitable for high-speed signal transmission.
Public/Granted literature
- US20100047967A1 METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE USING IMPROVED TECHNIQUE OF FORMING THROUGH VIA Public/Granted day:2010-02-25
Information query
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