Invention Grant
US07994051B2 Implantation method for reducing threshold voltage for high-K metal gate device
有权
用于降低高K金属栅极器件的阈值电压的植入方法
- Patent Title: Implantation method for reducing threshold voltage for high-K metal gate device
- Patent Title (中): 用于降低高K金属栅极器件的阈值电压的植入方法
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Application No.: US12253741Application Date: 2008-10-17
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Publication No.: US07994051B2Publication Date: 2011-08-09
- Inventor: Cheng-Lung Hung , Yong-Tian Hou , Keh-Chiang Ku , Chien-Hao Huang
- Applicant: Cheng-Lung Hung , Yong-Tian Hou , Keh-Chiang Ku , Chien-Hao Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.
Public/Granted literature
- US20100096705A1 IMPLANTATION METHOD FOR REDUCING THRESHOLD VOLTAGE FOR HIGH-K METAL GATE DEVICE Public/Granted day:2010-04-22
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