Invention Grant
- Patent Title: Stacked semiconductor device
-
Application No.: US11724303Application Date: 2007-03-15
-
Publication No.: US07994620B2Publication Date: 2011-08-09
- Inventor: Atsushi Yoshimura , Hideko Mukaida
- Applicant: Atsushi Yoshimura , Hideko Mukaida
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JPP2006-073142 20060316
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
A stacked semiconductor device includes a first semiconductor element bonded on a circuit base. The first semiconductor element is electrically connected to a connection part of the circuit base via a first bonding wire. A second semiconductor element is bonded on the first semiconductor element via a second adhesive layer with a thickness of 50 μm or more. The second adhesive layer is formed of an insulating resin layer whose glass transition temperature is 135° C. or higher and whose coefficient of linear expansion at a temperature equal to or lower than the glass transition temperature is 100 ppm or less.
Public/Granted literature
- US20070222051A1 Stacked semiconductor device Public/Granted day:2007-09-27
Information query
IPC分类: