Invention Grant
- Patent Title: Semiconductor device with offset stacked integrated circuits
- Patent Title (中): 具有偏移堆叠集成电路的半导体器件
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Application No.: US12167228Application Date: 2008-07-02
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Publication No.: US07994623B2Publication Date: 2011-08-09
- Inventor: Itaru Nonomura , Kenichi Osada , Makoto Saen
- Applicant: Itaru Nonomura , Kenichi Osada , Makoto Saen
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2007-185425 20070717
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L27/00

Abstract:
A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.
Public/Granted literature
- US20090021974A1 SEMICONDUCTOR DEVICE Public/Granted day:2009-01-22
Information query
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