Invention Grant
- Patent Title: Multi-layer semiconductor package with vertical connectors and method of manufacture thereof
- Patent Title (中): 具有垂直连接器的多层半导体封装及其制造方法
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Application No.: US12559432Application Date: 2009-09-14
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Publication No.: US07994626B2Publication Date: 2011-08-09
- Inventor: Rajendra D. Pendse
- Applicant: Rajendra D. Pendse
- Applicant Address: US CA Fremont
- Assignee: Stats Chippac, Inc.
- Current Assignee: Stats Chippac, Inc.
- Current Assignee Address: US CA Fremont
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/50

Abstract:
A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.
Public/Granted literature
- US20100007002A1 MULTI-LAYER SEMICONDUCTOR PACKAGE Public/Granted day:2010-01-14
Information query
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