Invention Grant
US07994645B2 Integrated circuit package system with wire-in-film isolation barrier
有权
集成电路封装系统，具有电线隔离屏障
- Patent Title: Integrated circuit package system with wire-in-film isolation barrier
- Patent Title (中): 集成电路封装系统，具有电线隔离屏障
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Application No.: US12169342Application Date: 2008-07-08
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Publication No.: US07994645B2Publication Date: 2011-08-09
- Inventor: Jonathan Abela
- Applicant: Jonathan Abela
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agent Mikio Ishimaru
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
An integrated circuit package in package system includes: providing a substrate having a first wire-bonded die with an active side mounted above; connecting the active side of the first wire-bonded die to the substrate with a bond-wire; mounting a wire-in-film adhesive having an isolation barrier over the first wire-bonded die; and encapsulating the first wire-bonded die, the bond-wires, and the wire-in-film adhesive with an encapsulation.
Public/Granted literature
- US20090014893A1 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER Public/Granted day:2009-01-15
Information query
IPC分类:
