Invention Grant
US07994812B2 Calibration circuit, semiconductor device including the same, and data processing system
有权
校准电路,包括相同的半导体器件和数据处理系统
- Patent Title: Calibration circuit, semiconductor device including the same, and data processing system
- Patent Title (中): 校准电路,包括相同的半导体器件和数据处理系统
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Application No.: US12654253Application Date: 2009-12-15
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Publication No.: US07994812B2Publication Date: 2011-08-09
- Inventor: Fumiyuki Osanai , Hiroki Fujisawa
- Applicant: Fumiyuki Osanai , Hiroki Fujisawa
- Applicant Address: JP Chuo-ku, Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Chuo-ku, Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007-176270 20070704
- Main IPC: H03K17/16
- IPC: H03K17/16

Abstract:
A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.
Public/Granted literature
- US20100097096A1 Calibration circuit, semiconductor device including the same, and data processing system Public/Granted day:2010-04-22
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