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US07994824B2 Logic gate with a reduced number of switches, especially for applications in integrated circuits 失效
具有减少数量的开关的逻辑门，特别是在集成电路中的应用

  • Patent Title: Logic gate with a reduced number of switches, especially for applications in integrated circuits
  • Patent Title (中): 具有减少数量的开关的逻辑门，特别是在集成电路中的应用
  • Application No.: US12742572
    Application Date: 2008-11-14
  • Publication No.: US07994824B2
    Publication Date: 2011-08-09
  • Inventor: Fabio Alessio Marino , Alessandro Paccagnella
  • Applicant: Fabio Alessio Marino , Alessandro Paccagnella
  • Applicant Address: US CA San Jose
  • Assignee: Fabio Alessio Narino
  • Current Assignee: Fabio Alessio Narino
  • Current Assignee Address: US CA San Jose
  • Agent Bryan W. Bockhop
  • Priority: ITPD2007A0381 20071114
  • International Application: PCT/IT2008/000711 WO 20081114
  • International Announcement: WO2009/063527 WO 20090522
  • Main IPC: H03K19/094
  • IPC: H03K19/094 ;  H03K19/20
Logic gate with a reduced number of switches, especially for applications in integrated circuits
Abstract:
Logic Gate (100), particularly for integrated circuits including a Boolean network (105) having at least an input (106) and having at least an output node (107) and at least a terminal (108) connected to a first node at fixed potential (109) corresponding to a first logical level of the gate. The gate is characterized by the fact that the output node (107) is connected to a first pair of switches including a first switch (101) and a second switch (102), which are activated alternately, and are connected respectively, by a respective terminal, to the first node (109) at fixed potential and to the output node (107). Between the two switches there is a second pair of switches (103, 104) connected to a second node at fixed potential (110) corresponding to a second logical level of the gate. The switches of the second pair of switches are connected together in a way that the turning on of one switch of the second pair involves the turning off of the other switch of the second pair and the turning on of one of the switches of the second pair is suitable to bring the output node (107) to the potential of the second node at fixed potential (110).
Abstract(Chinese):

逻辑门（100），特别是对于包括至少具有输入（106）并且至少具有输出节点（107）的至少一个终端（108）的布尔网络（105）的集成电路，所述终端连接到固定的第一节点 电位（109）对应于门的第一逻辑电平。 门的特征在于，输出节点（107）连接到包括第一开关（101）和第二开关（102）的第一对开关，其交替地被激活，并且分别由相应的 终端，到固定电位的第一节点（109）和输出节点（107）。 在两个开关之间存在第二对开关（103,104），其连接到对应于门的第二逻辑电平的固定电位（110）的第二节点。 第二对开关的开关以这样的方式连接在一起，使得第二对开关的一个开关的接通涉及第二对的另一开关的断开以及第二对开关中的一个开关的导通 适于将输出节点（107）带到固定电位（110）处的第二节点的电位。

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