A memory includes first and second select gate transistors, memory cells which are connected in series between the first and second select gate transistors, a selected word line which is connected to a selected memory cell as a target of a reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which changes a set up term of the selected word line and the non-selected word line based on a value of the selected read potential, wherein the value of the selected read potential is selected from two or more potentials.