Invention Grant
US07995394B2 Program voltage compensation with word line bias change to suppress charge trapping in memory
有权
程序电压补偿用字线偏置改变,以抑制存储器中的电荷捕获
- Patent Title: Program voltage compensation with word line bias change to suppress charge trapping in memory
- Patent Title (中): 程序电压补偿用字线偏置改变,以抑制存储器中的电荷捕获
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Application No.: US12512181Application Date: 2009-07-30
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Publication No.: US07995394B2Publication Date: 2011-08-09
- Inventor: Yingda Dong , Toru Ishigaki , Ken Oowada
- Applicant: Yingda Dong , Toru Ishigaki , Ken Oowada
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies Inc.
- Current Assignee: SanDisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus & DeNiro LLP
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.
Public/Granted literature
- US20110026331A1 PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY Public/Granted day:2011-02-03
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