Invention Grant
- Patent Title: Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
- Patent Title (中): 用于擦除在浮栅存储器单元上积分磁隧道结的半导体磁存储器的方法
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Application No.: US12966430Application Date: 2010-12-13
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Publication No.: US07995402B2Publication Date: 2011-08-09
- Inventor: Parag Banerjee , Terry Gafron , Fernando Gonzalez
- Applicant: Parag Banerjee , Terry Gafron , Fernando Gonzalez
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: G11C16/14
- IPC: G11C16/14

Abstract:
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
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