Invention Grant
US07995646B2 Communication test circuit, communication interface circuit, and communication test method 有权
通信测试电路,通信接口电路和通信测试方法

Communication test circuit, communication interface circuit, and communication test method
Abstract:
A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.
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