Invention Grant
- Patent Title: Communication test circuit, communication interface circuit, and communication test method
- Patent Title (中): 通信测试电路,通信接口电路和通信测试方法
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Application No.: US11898658Application Date: 2007-09-13
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Publication No.: US07995646B2Publication Date: 2011-08-09
- Inventor: Tetsuya Hayashi , Masanori Yoshitani , Tomokazu Higuchi
- Applicant: Tetsuya Hayashi , Masanori Yoshitani , Tomokazu Higuchi
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Staas & Halsey LLP
- Priority: JP2006-248073 20060913
- Main IPC: H04B17/00
- IPC: H04B17/00

Abstract:
A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.
Public/Granted literature
- US20080063127A1 Communication test circuit, communication interface circuit, and communication test method Public/Granted day:2008-03-13
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