First and second envelope detector circuits have, respectively, a resistance row, a capacitative element connected to the resistance row in parallel and a transistor connected between a connection point between the resistance row and the capacitative element and a predetermined voltage node. An output of a level shifter is supplied to a gate or a base of the transistor of the first envelope detector circuit. A predetermined voltage is supplied to a gate or a base of the transistor of the second envelope detector circuit. A detector detects an intermediate terminal voltage of the resistance row of the first envelope detector circuit with reference to a total voltage or an intermediate terminal voltage of the resistance row of the second envelope detector circuit.