Invention Grant
US07996193B2 Method for reducing model order exploiting sparsity in electronic design automation and analysis
失效
减少采用电子设计自动化和分析中稀疏性的模型顺序的方法
- Patent Title: Method for reducing model order exploiting sparsity in electronic design automation and analysis
- Patent Title (中): 减少采用电子设计自动化和分析中稀疏性的模型顺序的方法
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Application No.: US12106948Application Date: 2008-04-21
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Publication No.: US07996193B2Publication Date: 2011-08-09
- Inventor: Zuochang Ye , Zhenhai Zhu , Joel Phillips
- Applicant: Zuochang Ye , Zhenhai Zhu , Joel Phillips
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Dickstein Shapiro LLP
- Main IPC: G06F7/60
- IPC: G06F7/60

Abstract:
A method for reducing the order of system models exploiting sparsity is disclosed. According to one embodiment, a computer-implemented method receives a system model having a first system order. The system model contains a plurality of system nodes, a plurality of system matrices. The system nodes are reordered and a reduced order system is constructed by a matrix decomposition (e.g., Cholesky or LU decomposition) on an expansion frequency without calculating a projection matrix. The reduced order system model has a lower system order than the original system model.
Public/Granted literature
- US20090265150A1 METHOD FOR REDUCING MODEL ORDER EXPLOITING SPARSITY Public/Granted day:2009-10-22
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