Invention Grant
US07996614B2 Cache intervention on a separate data bus when on-chip bus has separate read and write data busses
有权
当片上总线具有单独的读写数据总线时，在单独数据总线上进行缓存干预
- Patent Title: Cache intervention on a separate data bus when on-chip bus has separate read and write data busses
- Patent Title (中): 当片上总线具有单独的读写数据总线时，在单独数据总线上进行缓存干预
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Application No.: US11969256Application Date: 2008-01-04
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Publication No.: US07996614B2Publication Date: 2011-08-09
- Inventor: Robert Michael Dinkjian , Bernard Charles Drerup
- Applicant: Robert Michael Dinkjian , Bernard Charles Drerup
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yee & Associates, P.C.
- Agent Thomas E. Tyson
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28
Abstract:
Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.
Public/Granted literature
- US20090177821A1 Cache Intervention on a Separate Data Bus When On-Chip Bus Has Separate Read and Write Data Busses Public/Granted day:2009-07-09
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