Invention Grant
- Patent Title: K-way direct mapped cache
- Patent Title (中): K路直接映射缓存
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Application No.: US10831488Application Date: 2004-04-22
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Publication No.: US07996619B2Publication Date: 2011-08-09
- Inventor: Kiran R. Desai
- Applicant: Kiran R. Desai
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way within a plurality based on a first portion of the address. The control logic may match the first portion of the address to a predefined value in a mapping table, wherein the predefined value in the mapping table is associated with the way. In addition, the control logic may map the address to a set within cache based on a second portion of the address.
Public/Granted literature
- US20050240715A1 K-way direct mapped cache Public/Granted day:2005-10-27
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