Invention Grant
- Patent Title: High performance pseudo dynamic 36 bit compare
- Patent Title (中): 高性能伪动态36位比较
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Application No.: US11850050Application Date: 2007-09-05
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Publication No.: US07996620B2Publication Date: 2011-08-09
- Inventor: Yuen H. Chan , Ann H. Chen , Kenneth M. Lo , Shie-ei Wang
- Applicant: Yuen H. Chan , Ann H. Chen , Kenneth M. Lo , Shie-ei Wang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent William A. Kinnaman, Jr.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G11C15/00 ; G11C7/06 ; G11C7/10
Abstract:
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.
Public/Granted literature
- US20090063774A1 High Performance Pseudo Dynamic 36 Bit Compare Public/Granted day:2009-03-05
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