Invention Grant
US07996625B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
有权
用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
- Patent Title: Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
- Patent Title (中): 用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
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Application No.: US11790989Application Date: 2007-04-30
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Publication No.: US07996625B2Publication Date: 2011-08-09
- Inventor: Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
- Applicant: Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00
Abstract:
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
Public/Granted literature
- US20070204111A1 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture Public/Granted day:2007-08-30
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