Invention Grant
US07996642B1 Digital locked loop on channel tagged memory requests for memory optimization 有权
数字锁定环通道标记内存请求进行内存优化

  • Patent Title: Digital locked loop on channel tagged memory requests for memory optimization
  • Patent Title (中): 数字锁定环通道标记内存请求进行内存优化
  • Application No.: US12107694
    Application Date: 2008-04-22
  • Publication No.: US07996642B1
    Publication Date: 2011-08-09
  • Inventor: Ronald Smith
  • Applicant: Ronald Smith
  • Applicant Address: BM
  • Assignee: Marvell International Ltd.
  • Current Assignee: Marvell International Ltd.
  • Current Assignee Address: BM
  • Main IPC: G06F12/00
  • IPC: G06F12/00
Digital locked loop on channel tagged memory requests for memory optimization
Abstract:
A method and system for performing memory optimization. The method includes receiving from a processor a plurality of read/write requests, wherein at least a portion of the read/write requests are assigned respective identifiers for associating related ones of the read/write requests; measuring arrival times of the read/write requests assigned to each of the identifiers; determining a periodicity and a phase of the read/write requests based on the identifiers in order to determine predicted arrival times of future read/write requests assigned to each of the identifiers; creating a real-time schedule of memory requests using the arrival times of the read/write requests and the predicted arrival times of the future read/write requests; using the real-time schedule to determine idle periods where none of the read/write requests will be received; and performing opportunistic functions during the idle periods, including performing at least one of garbage collection and translation cache pre-fetch.
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