A processor architecture includes a plurality of elements arranged in an array of rows and columns and a plurality of first and second bus pairs with the first pair being located between different adjacent rows of the array and having first and second buses running in opposite directions and the second bus pair being located between different adjacent columns of the array and having third and fourth buses running in opposite directions and intersecting the first and second buses. A plurality of switch matrices located at an intersection of one of the first bus pairs and one of the second bus pairs includes inputs and outputs for first, second, third and fourth buses and switch elements for switchably connecting the inputs and outputs.