Invention Grant
- Patent Title: Signal bus, multilevel input interface and information processor
- Patent Title (中): 信号总线,多电平输入接口和信息处理器
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Application No.: US12001911Application Date: 2007-12-13
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Publication No.: US07996705B2Publication Date: 2011-08-09
- Inventor: Kesatoshi Takeuchi
- Applicant: Kesatoshi Takeuchi
- Applicant Address: JP
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2006-336493 20061214; JP2007-286031 20071102
- Main IPC: G06F1/04
- IPC: G06F1/04 ; H03K3/00

Abstract:
A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal indicating the timings of reading level information for the M-level signal, includes: a threshold value generation unit that produces a plurality of voltage outputs as a plurality of variable comparison reference signals according to the level-varying supply voltage; a level detection unit that compares, in synchronization with the transmission clock signal, the M-value level signal with the variable comparison reference signals and generates a logic output corresponding to an instantaneous value of the M-level signal; and a logic circuit unit that converts the logic output to a data signal.
Public/Granted literature
- US20080148091A1 Signal bus, multilevel input interface and information processor Public/Granted day:2008-06-19
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