Invention Grant
- Patent Title: Defect management for a semiconductor memory system
- Patent Title (中): 半导体存储器系统的缺陷管理
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Application No.: US11740052Application Date: 2007-04-25
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Publication No.: US07996710B2Publication Date: 2011-08-09
- Inventor: Dheemanth Nagaraj , Larry J. Thayer
- Applicant: Dheemanth Nagaraj , Larry J. Thayer
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
Public/Granted literature
- US20080270675A1 DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM Public/Granted day:2008-10-30
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