Invention Grant
US07996742B2 Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement
有权
用于检查电路布置中的逻辑电路的功能的电路布置和方法
- Patent Title: Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement
- Patent Title (中): 用于检查电路布置中的逻辑电路的功能的电路布置和方法
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Application No.: US12268226Application Date: 2008-11-10
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Publication No.: US07996742B2Publication Date: 2011-08-09
- Inventor: Marcus Janke , Franz Klug , Peter Laackmann , Dirk Rabe , Stefan Rueping
- Applicant: Marcus Janke , Franz Klug , Peter Laackmann , Dirk Rabe , Stefan Rueping
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Dickstein Shapiro LLP.
- Priority: DE102007053295 20071108
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A circuit arrangement comprising a logic circuit to be tested and a test circuit. The logic circuit comprising logic-circuit-internal combinations configured to generate output data from input data based on a predetermined relationship. The logic circuit is configured to detect whether the relationship is satisfied and to provide an error signal if the relationship is not satisfied. The test circuit is configured to alter logic-circuit-internal combinations, to detect the error signal, and to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations.
Public/Granted literature
- US20090172489A1 CIRCUIT ARRANGEMENT AND METHOD FOR CHECKING THE FUNCTION OF A LOGIC CIRCUIT IN A CIRCUIT ARRANGEMENT Public/Granted day:2009-07-02
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