Invention Grant
US07996745B2 ECC for single 4-bits symbol correction of 32 symbols words with 21 maximum row weight matrix
有权
用于具有21个最大行权重矩阵的32个符号字的单个4位符号校正的ECC
- Patent Title: ECC for single 4-bits symbol correction of 32 symbols words with 21 maximum row weight matrix
- Patent Title (中): 用于具有21个最大行权重矩阵的32个符号字的单个4位符号校正的ECC
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Application No.: US11437273Application Date: 2006-05-19
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Publication No.: US07996745B2Publication Date: 2011-08-09
- Inventor: Antonio Griseta , Antonio Lonigro , Angelo Mazzone
- Applicant: Antonio Griseta , Antonio Lonigro , Angelo Mazzone
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Graybeal Jackson LLP
- Agent Lisa K. Jorgenson; Kevin D. Jablonski
- Priority: EP05104238 20050519; EP05104239 20050519
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.
Public/Granted literature
- US20070016843A1 ECC for single 4-bits symbol correction of 32 symbols words with 21 maximum row weight matrix Public/Granted day:2007-01-18
Information query
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