Invention Grant
US07996805B2 Method of stitching scan flipflops together to form a scan chain with a reduced wire length
有权
将扫描触发器拼接在一起以形成具有减少的线长度的扫描链的方法
- Patent Title: Method of stitching scan flipflops together to form a scan chain with a reduced wire length
- Patent Title (中): 将扫描触发器拼接在一起以形成具有减少的线长度的扫描链的方法
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Application No.: US12008163Application Date: 2008-01-08
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Publication No.: US07996805B2Publication Date: 2011-08-09
- Inventor: Ronald Pasqualini
- Applicant: Ronald Pasqualini
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Mark C. Pickering
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The scan flipflops on a semiconductor chip are stitched together to form one or more scan chains, located in one or more standard cell placement regions, after the optimal physical location of each scan flip-flop has been determined. As a result, the total length of the scan chain wires is substantially reduced, thereby reducing on-chip wiring congestion, flip-flop load capacitance, and flipflop power dissipation.
Public/Granted literature
- US20090174451A1 Method of stitching scan flipflops together to form a scan chain with a reduced wire length Public/Granted day:2009-07-09
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