Invention Grant
US07996813B2 Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program
有权
用于生成图案的方法,制造半导体器件的方法,半导体器件和计算机程序
- Patent Title: Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program
- Patent Title (中): 用于生成图案的方法,制造半导体器件的方法,半导体器件和计算机程序
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Application No.: US12654865Application Date: 2010-01-07
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Publication No.: US07996813B2Publication Date: 2011-08-09
- Inventor: Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
- Applicant: Masaaki Hatano , Motoya Okazaki , Junichi Wada , Takeshi Nishioka , Hisashi Kaneko , Takeshi Fujimaki , Kazuyuki Higashi , Kenji Yoshida , Noriaki Matsunaga
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JPP2004-322170 20041105
- Main IPC: G06F15/04
- IPC: G06F15/04

Abstract:
A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
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