Invention Grant
- Patent Title: Fabrication methods for integration CMOS and BJT devices
- Patent Title (中): 集成CMOS和BJT器件的制作方法
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Application No.: US12323404Application Date: 2008-11-25
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Publication No.: US08008212B2Publication Date: 2011-08-30
- Inventor: Chien-Hsien Song , Yung-Lung Chou , Yu-Hsun Chen , Cheng-Che Tsai
- Applicant: Chien-Hsien Song , Yung-Lung Chou , Yu-Hsun Chen , Cheng-Che Tsai
- Applicant Address: TW Hsinchu
- Assignee: Vanguard International Semiconductor Corporation
- Current Assignee: Vanguard International Semiconductor Corporation
- Current Assignee Address: TW Hsinchu
- Priority: TW97130647A 20080812
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.
Public/Granted literature
- US20100041233A1 FABRICATION METHODS FOR INTEGRATION CMOS AND BJT DEVICES Public/Granted day:2010-02-18
Information query
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