Invention Grant
- Patent Title: Semiconductor memory structure with stress regions
- Patent Title (中): 具有应力区域的半导体存储器结构
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Application No.: US12233486Application Date: 2008-09-18
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Publication No.: US08008692B2Publication Date: 2011-08-30
- Inventor: Hung-Wei Chen , Yider Wu
- Applicant: Hung-Wei Chen , Yider Wu
- Applicant Address: TW Hsin-Chu
- Assignee: EON Silicon Solution Inc.
- Current Assignee: EON Silicon Solution Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: Schmeiser, Olsen & Watts LLP
- Main IPC: H01L29/04
- IPC: H01L29/04

Abstract:
A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.
Public/Granted literature
- US20100065893A1 SEMICONDUCTOR MEMORY STRUCTURE WITH STRESS REGIONS Public/Granted day:2010-03-18
Information query
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