Invention Grant
- Patent Title: Semiconductor device including a plurality of diffusion layers and diffusion resistance layer
- Patent Title (中): 半导体器件包括多个扩散层和扩散电阻层
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Application No.: US12379510Application Date: 2009-02-24
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Publication No.: US08008723B2Publication Date: 2011-08-30
- Inventor: Takayuki Nagai
- Applicant: Takayuki Nagai
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-083700 20080327
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
Aimed at reducing the area of a protective circuit in a semiconductor device provided therewith, a semiconductor device of the present invention has a first-conductivity-type well, a plurality of first diffusion layers formed in the well, a plurality of second diffusion layers formed in the well, and a diffusion resistance layer formed in the well, wherein the first diffusion layers have a second conductivity type, and are connected in parallel with each other to an input/output terminal of the semiconductor device; the second diffusion layers are arranged alternately with a plurality of first diffusion layers, and are connected to a power source or to the ground; the diffusion resistance layer has a second conductivity type, and is located in adjacent to any of the plurality of second diffusion layers; the diffusion resistance layer is connected to the input/output terminal of the semiconductor device, while being arranged in parallel with the first diffusion layers, and connects the internal circuit and the input/output terminal of the semiconductor device.
Public/Granted literature
- US20090242991A1 Semiconductor device Public/Granted day:2009-10-01
Information query
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