A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. Pattern P1a is formed in the same layer as a second layer wiring, pattern P1b is formed in the same layer as a first layer wiring, pattern P2 is formed in the same layer as a gate electrode, and pattern P3 is formed in the same layer as an element isolation region.