Invention Grant
- Patent Title: Circuit board test system and test method
- Patent Title (中): 电路板测试系统和测试方法
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Application No.: US12379359Application Date: 2009-02-19
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Publication No.: US08008940B2Publication Date: 2011-08-30
- Inventor: Nobuyuki Takase
- Applicant: Nobuyuki Takase
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-044381 20080226
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
A circuit board system is adapted to check a DUT (Device Under Test) and a communication device on a DUT board, check the connection between DUT and communication device and check connections of parts mounted on DUT board. The system, which tests a circuit board used when a DUT is tested using a tester, has a socket into which DUT is removably inserted; a communication device mounted thereon; first wires electrically connecting first signal terminals of DUT and the tester; and second wires electrically connecting second signal terminals of DUT, which are not electrically connected to the first signal terminals, and signal terminals of the communication device. A shorting board is inserted into the socket in place of DUT when the circuit board is tested, the shorting board having short-circuit wires electrically connecting the first wires and the second wires.
Public/Granted literature
- US20090267628A1 Circuit board test system and test method Public/Granted day:2009-10-29
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