Invention Grant
- Patent Title: High voltage switch utilizing low voltage MOS transistors with high voltage breakdown isolation junctions
- Patent Title (中): 高压开关利用具有高压击穿隔离结的低压MOS晶体管
-
Application No.: US12555259Application Date: 2009-09-08
-
Publication No.: US08008951B2Publication Date: 2011-08-30
- Inventor: Tacettin Isik
- Applicant: Tacettin Isik
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology, Inc.
- Current Assignee: Integrated Device Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Panitch, Schwarze, et al.
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.
Public/Granted literature
Information query