Invention Grant
- Patent Title: Flip-flop circuit that latches inputted data
- Patent Title (中): 锁存输入数据的触发器电路
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Application No.: US12371094Application Date: 2009-02-13
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Publication No.: US08008959B2Publication Date: 2011-08-30
- Inventor: Satoru Sekine , Shinji Furuichi
- Applicant: Satoru Sekine , Shinji Furuichi
- Applicant Address: JP Osaka
- Assignee: Sanyo Electric Co., Ltd.
- Current Assignee: Sanyo Electric Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2008-068168 20080317
- Main IPC: H03K3/289
- IPC: H03K3/289

Abstract:
A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude.
Public/Granted literature
- US20090231008A1 FLIP-FLOP CIRCUIT THAT LATCHES INPUTTED DATA Public/Granted day:2009-09-17
Information query
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